Industrial users of dynamic random access memories (DRAMs) are demanding ever-quicker timing and ever-smaller power specifications. To meet these specifications, designers must design DRAMs to read from and write to the DRAM storage cells more and more quickly while at the same time using less power. This requires that improved methods be discovered to drive DRAM word lines (also referred to as "row" lines in the art) to a voltage supply source Vdd during the precharge portion of the reading cycle and to boot them above V.sub.dd during the active restore portion of the cycle. These functions are a substantial part of an active cycle's length.
A selected word line is driven for reading, and is booted for the active restore function, using a drive/boot signal transmitted from a drive/boot signal generator conventionally located in a peripheral area of the chip. An increasing importance has been placed on the decoding path of this drive/boot signal from the drive/boot generator to the active word lines. If this decoding path is too resistive or capacitive, the driving and booting of the word lines will be too slow. In addition, if the drive/boot signal path is too capacitive, the device will use too much power.
To illustrate the disadvantages of present drive/boot signal decoding systems, two examples will be described. In a pair of conventional 64 K and 256 K DRAM designs, one drive/boot generator is provided. Its output is split into two separate global signal lines (that is, signal lines that extend over the entire array) using pass gates. Therefore, only one of the split lines is required to be active in any given cycle. Each of the split lines then connects to one-half of all of the word line drivers or decoders in the DRAM in order to drive and boot the appropriate word lines. The row decoders are selected by addressing signals. Thus, in any given cycle, the one master drive/boot signal will "see" the parasitic capacitance of one-half of all of the word line drivers on the entire chip connected to it, plus the parasitic capacitance of two extra decoding pass gates. In addition to the relatively large amount of capacitance that this creates, the drive/boot signal is required to travel through the resistance of one pass gate and one word line driver to get to each decoded word line.
According to another conventional design used in 256 K and 1 M Complementary Metal Oxide Semiconductor (CMOS) DRAMs, four drive/boot generators are provided with four separate global drive/boot signal lines. Only one of these signal lines is active for any given cycle. Each drive/boot signal line is directly connected to one-fourth of all of the word line drivers on the chip. The four generators used according to this method require more space on the chip than one large signal generator. Further, each of the four drive/boot signal lines is heavily loaded with one-fourth of the entire chip's word line drivers parasitic capacitance. Each drive/boot signal must furthermore travel through the resistance of one word line driver to reach each word line.
The above conventional drive/boot signal decoding solutions require that the drive/boot signal "see" an undesirably large amount of parasitic capacitance, thus slowing down cycle times. The importance of minimizing this capacitance increases with increasing cycle speed, smaller voltage differences and larger array sizes such as are mandated for the 4 M DRAM. A need has therefore arisen for a drive/boot signal decoding scheme that will result in improved parasitic capacitance characteristics.